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07-01-2017, 03:18 PM
Post: #1
intel 8086 opcode sheet pdf

please give the op code sheet in 8 - bit Intel microprocessor. For my practical purpose .
08-02-2017, 03:10 PM
Post: #2
RE: intel 8086 opcode sheet pdf
This is an HTML-ized version of the operating-code map for the 8086 processor. It is based on the opcode map in Appendix A of Volume 2 of the Intel Architecture Software Developer's Handbook. Also available is a plain text version, easily scalable by software.
This map was built by taking a map for a newer x86 processor and removing irrelevant information for the 8086 processor (long before). I wanted a map as simple as possible, and to that end, this map contains some gaps:
* Opcodes D8 to DF - co-processor exhaust opcodes - here are treated as undefined opcodes. I wanted to focus the entire opcodes on this map, since the floating point would be extremely rare in production code 8086.
* Opcode 0F - "POP CS" on 8086, and the first byte in multi-byte opcodes on subsequent processors - is also treated as an undefined opcode. I would not expect to see this in code 8086 (as the "POP CS" instruction is particularly useless) and wanted to treat its appearance as an error condition.
* Opcodes C6, C7, and 8F require that the reg bits of the ModR / M byte following them are equal to zero. Other values ​​are illegal. This restriction is not shared with other opcodes with "E" arguments, and is not reflected on the map.
* Arguments are not given for a large number of opcodes (eg A4 to A7, 9C, 9D) that correspond to statements that do not take arguments when they are written as assembly code (eg MOVSB, MOVSW, CMPSB, CMPSW, PUSHF , POPF). I want to use this map to build a disassembler, not a dummy processor, and the additional arguments would only be heavy.
In addition to the information that has been deleted, this map contains two known errors. These were intentionally added so that the results of the disassembly based on this map would reflect the output of DOS DEBUG:

* Opcode 84 must have Eb, Gb - not Gb, Eb arguments. This distinction only affects (un) assembly, since the order of operands is irrelevant to the TEST function. However, DOS DEBUG has backwards, and duplicate the error here.
* Opcode 85 must have arguments of Ev, Gv - not Gv, Ev. All previous observations on the operation code 84 are equally applicable here.
To use the map, find the cell in the row marked with the 4 most significant bits of the operation code and the column labeled with the 4 least significant bits of the operation code. (The map is divided by half, columns 0-7 appear in the first part, while columns 8-F appear in the second.) For example, opcode 23 appears in the 3rd row, 4th column of the first Part of the map Y Gv, Ev). Operation code 4E appears in the 5th row, 7th column of the second part of the map (DEC SI).

Arguments are a pair of letters - the first in capital letters, the second in lowercase - or a special symbol. A case-sensitive pair can be interpreted by looking at the uppercase in the "Array Address Codes" table and the lowercase letter in the "Array Operand Codes" table. Other special symbols can be found in the "Special argument codes" table.

Continuing with the previous example, opcode 23 is resolved in an AND instruction Gv, Ev. Both arguments are case-sensitive. G represents a general purpose register selected by the reg bits of a ModR / M byte after the operation code byte. E represents a memory location or a general purpose register selected by the mod and r / m bits of a ModR / M byte after the operation code byte. Both operands are of type "v", so both are WORD. Hence, operation code 23 takes the logical AND of a WORD from a 16-bit register or memory location with the WORD of a 16-bit register and stores the result in the last record. The particular register and / or memory location involved can be determined by examining the ModR / M byte following the operation code and referring to page 2-5 of the Instruction Set Reference.

Operation code 4E, on the other hand, resolves a DEC SI instruction. The SI argument is not a case-sensitive pair, so we check the special code table. IF it turns out (as expected) the 16-bit SI register, so operation code 4E simply decrements this register by 1. (Yes, with almost 30 years of hindsight, there probably should not be a complete operation code Dedicated to this operation.)
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